Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning”direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5-10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
Lithographic methods aimed at improving resolution, while retaining acceptable process latitude and robustness are classified as Resolution Enhancement Techniques (RET's) and comprise a very wide range of applications. As is known, printing mask features at near or below half of the optical exposure wavelength requires applying such resolution enhancement techniques, such as, for example, off-axis illumination (OAI), phase shift masks (PSM) and optical proximity correction (OPC) in combination with the use of a very high numerical aperture (NA>0.7).
However, while such techniques can be utilized to print sub-wavelength patterns, problems remain. As mentioned, the use of OAI is one technique that has been demonstrated and utilized successfully for improving the resolution for dense pitch features. However to date, this technique has been shown to severely degrade the imaging of isolated geometries in the case of both dark-field and bright-field mask types. Thus, the OAI technique by itself is unsuitable for printing random pitch features (i.e., features ranging from isolated to densely spaced). Sub-resolution assist features (SRAF, also known as scattering bars, SBs) have also been used to improve the printing of isolated features. By placing SBs adjacent to isolated features in a clear-field mask type, it makes the isolated feature behave as a dense feature, thereby achieving the improved printing performance when exposed under OAI. To date, the placement of SBs has been done by applying empirical rules. However, for semi-isolated or intermediate-pitch random features, the SB placement rules often need to be compromised mainly due to a lack of sufficient space for SB placement. Similarly, while adding anti-scattering bars (i.e., an anti-scattering bar is a bright mask feature that is applied on a dark-field mask, whereas a scatter bar is a dark feature applied in a clear field mask) to a mask design can improve the imaging for dark-field mask types, applying such anti-scattering bars through pitch and on random geometry has proved problematic. The problem becomes worse when utilizing attenuated PSM. This is due to much stronger optical proximity effect as compare to non-phase shifted mask type. The stronger optical proximity effect results in the through-pitch printing issues becoming much more severe. Thus, in order to. satisfactorily extend the printing resolution for deep sub-wavelength features, it is necessary to go beyond the present rule-based SB method for both non-phase-shifted and phase-shifted mask types.
Accordingly, there exists a need for a method of applying OPC to a mask layout which allows for the printing of deep sub-wavelength features through pitch, and which cures the deficiencies and problems associated with the prior art RET techniques noted above.